1. Field of the Invention
The present invention relates to a method for fabricating semiconductor devices, and more particularly to a method for forming an element isolating film appropriate for the fabrication of highly integrated semiconductor devices.
2. Description of the Prior Art
Typically, a semiconductor device is defined with active regions, on which individual elements are formed, and element isolating regions each serving to isolate adjacent active regions from each other.
Element isolating regions of such a semiconductor device electrically and structurally isolate individual elements constituting the semiconductor device from one another so that those elements can perform given functions without being affected by elements adjacent thereto.
In order to obtain a highly integrated semiconductor device, it is necessary to not only reduce the size of elements constituting the semiconductor device, but also to reduce the width and area of element isolating regions, namely, the width and area of an element isolating insulating film.
In this regard, element isolation techniques are techniques for determining memory cell size.
Element isolation techniques at the early development stage are those using a junction isolation method for the fabrication of bipolar integrated devices.
At present, element isolation techniques are those using a local oxidation of silicon (LOCOS) method, which is an insulator isolating method, and those using a trenching method, which is an insulator burying method, for the fabrication of MOS IC's, namely, LSI's and VLSI's.
The LOCOS method is for isolating adjacent elements by forming a thick element isolating insulating film between adjacent active regions defined on a semiconductor substrate using an insulating film, such as a silicon nitride film, as a mask.
A conventional method for forming an element isolating film of a semiconductor device in accordance with the LOCOS method will be described in conjunction with FIGS. 1 to 4.
FIGS. 1 to 4 are sectional views respectively illustrating sequential steps of the method for forming an element isolating film in accordance with the LOCOS method.
In accordance with this method, a pad oxide film 3 and a nitride film 5 are first formed to desired thicknesses over a semiconductor substrate 1 in a sequential manner, as shown in FIG. 1.
A photoresist film pattern 7 is then formed on the nitride film 5 to define an element isolating region.
Thereafter, the nitride film 5 and pad oxide film 3 are etched using the photoresist film pattern 7 as a mask, as shown in FIG. 2. The photoresist film pattern 7 is then removed, thereby forming a contact hole 9 exposing a portion of the semiconductor substrate 1 corresponding to a field region on which an element isolating insulating film will be formed.
The resulting structure is then subjected to a thermal oxidation process, namely, a field oxidation process. That is, a thermal oxide film 11 is formed on the portion of the semiconductor substrate 1 exposed through the contact hole 9, as shown in FIG. 3.
At this time, the nitride film 5 is partially lifted at its edges due to the growth of the thermal oxide film 11.
Subsequently, the nitride film 5 and pad oxide film 3 are completely removed. Thus, an element isolating insulating film 13 is formed, as shown in FIG. 4.
Referring to FIG. 4, it can be found that the element isolating insulating film 13 has elongated bird's beaks A at its edges.
However, the above-mentioned element isolating film forming method has the following problems.
In accordance with the above-mentioned conventional method, the portion of the element isolating insulating film buried in the semiconductor substrate has a volume ratio (thickness ratio) of only about 50%. This results in a low punch-through voltage and a deteriorated planarization. As a result, there is difficulty in performing subsequent processes.
In accordance with the conventional method, a bird's beak phenomenon occurs in the thermal oxidation process. That is, the edge portion of the element isolating insulating film penetrates active regions. This results in a reduction in the area of active regions. As a result, it is difficult to achieve a high integration of the semiconductor device.
Where a channel stopper is provided by injecting ions between adjacent element isolating insulting films to prevent a reduction in punch-through voltage between adjacent active regions, an increase in junction leakage current occurs. This results in a reduction in channel width. Consequently, there is a degradation in the electrical characteristic and reliability of the semiconductor device.
In accordance with the conventional method, the element isolating insulating film protrudes from the semiconductor substrate, thereby forming steps. As a result, an irregular reflection of light occurs in a subsequent lithography process, thereby generating a notching phenomenon. That is, a bad pattern is formed because the pattern is partially lost. This results in a deterioration in the operation characteristic and reliability of the semiconductor device. Consequently, process yield is reduced.